Prismora ECE Virtual Laboratory
Explore, construct, simulate, and verify electronic circuits, digital logic architectures, communication channels, and signal processing algorithms with mathematically rigorous analytical solvers and real-time observability.
Flagship Interactive Simulators
ECE Circuit Construction Studio & Virtual Arduino Uno R3
Design, wire, and simulate complete AC and DC circuits with realistic components or 2D KiCad-style PCB soldermask. Execute genuine C++ microcode on a virtual ATmega328P microcontroller with digital and PWM analog pins, live Serial Monitor, 4-band resistor color decoder, glowing filaments, spinning DC motors, SG90 servo angle sweep, and dual-channel oscilloscope traces.
Half & Full Adder Virtual Lab
Interactive 2D schematic canvas, logic gates, real-time wire routing, automated truth table verification, multi-channel logic analyzer, and comprehensive theory drawer.
Ohm's Law & DC Circuits Lab
0-30V DC bench supply, SPST knife switch lever, physics-driven incandescent tungsten bulb glow, 4-band EIA resistors, dynamic V-I scatter plot, and interactive multimeter.
PN Junction Diode & Rectifiers Lab
Shockley equation solver, Silicon vs Germanium knee curve sweep, Half-Wave & Bridge rectifiers, dual-trace oscilloscope graticule, and capacitor smoothing filter.
Digital Electronics & Logic Design Workbench
Scientifically verified discrete logic laboratory featuring 7 primitive gates, interactive truth tables, Quine-McCluskey K-map minimization, 4-bit ripple adders and ALUs, sequential flip-flops (SR, JK, D, T), synchronous counters, and static 1-hazard waveforms.
Network Theorems Lab: Thévenin, Norton & Maximum Power
Scientifically verified circuit reduction workbench. Compute open-circuit voltage Voc = Vth, internal de-energized resistance Rin = Rth, Norton current In = Vth/Rth, and swept load resistance dynamic power transfer curve (PL vs RL peak at RL = Rth).
ECE Circuit Studio & Virtual Arduino Uno (TinkerCAD + PhET DC/AC)
Interactive electronic circuit designer and embedded hardware studio. Features Lifelike, Schematic, and PCB view modes, AC/DC sources, 4-band resistor color decoder, glowing filaments, spinning DC motors, SG90 servo angle sweep, and a Virtual Arduino Uno R3 ATmega328P C++ execution engine with live Serial Monitor.
Ohm's Law & DC Electrical Circuits Laboratory
Explore voltage, current, and resistance in DC networks with variable bench power supply, real-time V-I scatter plotting, incandescent bulb filament glow, and digital multimeter probing.
Series Resistor Networks & Voltage Division
Equivalent resistance of series-connected resistors, cumulative voltage drop, and proportional voltage division.
Parallel Resistor Networks & Current Division
Equivalent conductance and current splitting across parallel resistor branches under constant node potential.
Series-Parallel Combination Resistor Networks
Reduction of complex resistive bridge networks using successive series and parallel equivalence transformations.
Kirchhoff's Current Law (KCL) Junction Analysis
Conservation of electric charge at electrical circuit nodes where algebraic sum of all currents equals zero.
Kirchhoff's Voltage Law (KVL) Closed Loop Analysis
Conservation of energy along any closed loop in a circuit, confirming total potential rise equals total potential drop.
Voltage Divider Circuits & Potentiometer Loading
Loaded vs unloaded voltage dividers, potentiometer wiper control, and finite input impedance loading effects.
Current Divider Circuits & Shunt Resistors
Current division between parallel branches and design of ammeter shunt resistors for range extension.
Electrical Power, Energy Dissipation & Joule Heating
Power dissipation in resistors, Joules law thermal heating, kilowatt-hour accumulation, and component wattage ratings.
Thevenin's Theorem & Equivalent Circuit Extraction
Transforming any linear bilateral two-terminal resistive network into an equivalent voltage source V_th in series with R_th.
Norton's Theorem & Dual Current Equivalent
Reduction of two-terminal linear circuits to a single Norton current source I_N in parallel with Norton resistance R_N.
Superposition Theorem in Multi-Source DC Networks
Analyzing linear circuits with multiple independent voltage and current sources by summing individual responses.
Maximum Power Transfer Theorem in DC Circuits
Condition for maximum power transfer from source to load (R_L = R_th) and efficiency vs power trade-off.
Source Transformation (Thevenin to Norton Dual)
Equivalence between practical voltage source (V_s in series with R_s) and practical current source (I_s in parallel with R_s).
Mesh Current Analysis & Planar Loop Equations
Formulating and solving matrix equations for planar circuits using fictitious circulating mesh currents.
Nodal Voltage Analysis & Conductance Matrix
Modified Nodal Analysis (MNA) using reference ground and node voltages to solve arbitrary circuit graphs.
Wheatstone Bridge & Precision Resistance Measurement
Null-deflection measurement of unknown resistors using balanced four-arm bridge topology.
Delta-Wye (Pi-T) Network Transformation
Transformation between 3-terminal Delta (triangle) and Star (Y) resistor topologies to simplify non-bridge networks.
AC Impedance, Phasors & Complex Reactance
Complex impedance Z = R + jX, inductive reactance X_L = 2pi*f*L, capacitive reactance X_C = 1/(2pi*f*C), and rotating phasors.
AC Power, Power Factor & Reactive Compensation
Active power (P), reactive power (Q), apparent power (S), power factor (cos phi), and capacitor power factor correction.
Series & Parallel RLC Resonance (Q-Factor & Bandwidth)
Resonant frequency f_0 = 1/(2pi*sqrt(LC)), impedance minimum/maximum, quality factor Q, and -3dB half-power bandwidth.
RC Circuit Transient Charging & Discharging Response
First-order transient exponential charging and discharging curves with time constant tau = R*C and step response.
RL Circuit Transient Inductor Current Response
Inductor current continuity, back-EMF spikes during disconnection, and exponential settling with time constant tau = L/R.
RLC Transient Damping (Overdamped, Critical, Underdamped)
Second-order differential equation response with variable damping ratio zeta: underdamped oscillations, critical damping, and overdamped decay.
Practical Voltage and Current Measurements (Meter Loading)
Internal resistance of practical voltmeters and ammeters, insertion errors, and measurement correction factors.
PN-Junction Diode I-V Characteristics & Knee Voltage
Forward and reverse DC bias characteristics of Silicon and Germanium diodes, Shockley equation modeling, knee voltage (0.7V / 0.3V), and dynamic resistance.
Forward and Reverse Diode Bias Dynamics
Depletion region width modulation, majority carrier diffusion under forward bias, and drift current saturation under reverse bias.
Half-Wave Rectifier Circuit with Dual-Trace Scope
AC to DC conversion using single-diode half-wave rectifier, peak output voltage, DC average calculation, and dual-channel waveform observation.
Full-Wave Center-Tapped Transformer Rectifier
Two-diode full-wave rectifier using center-tapped secondary winding, producing 2*f_in ripple frequency and higher DC efficiency.
Full-Wave Bridge Rectifier (4-Diode Diamond Topology)
Four-diode bridge rectifier delivering full-wave DC output without center-tapped transformer, 2*V_F forward drop, and PIV = V_m.
Capacitor-Filtered Rectifier & DC Smoothing
Shunt capacitor filter across rectifier load, ripple voltage reduction, conduction angle narrowing, and surge current spikes.
Ripple Factor & Rectification Efficiency Analysis
Systematic comparison of unfiltered vs LC vs Pi-filter networks on DC power supply quality.
Zener Diode Voltage Regulation & Line/Load Regulation
Zener reverse breakdown voltage clamping, series current-limiting resistor design, line regulation, and load regulation limits.
Diode Clipper Circuits (Positive, Negative, Biased Shunt)
Waveform shaping using series and shunt diode clippers with DC reference bias voltages to truncate voltage peaks.
Diode Clamping Circuits (DC Level Restorers)
Capacitor-diode clamping networks that shift AC signals to a new positive or negative DC reference level without altering peak-to-peak amplitude.
Light Emitting Diode (LED) Current Limiting & Efficiency
Forward voltage drop across various LED colors (Red, Green, Blue, White), luminous intensity, and series ballast resistor calculation.
BJT Common-Emitter Input Characteristics (I_B vs V_BE)
NPN Bipolar Junction Transistor base-emitter junction input family curves with collector-emitter voltage parameter V_CE.
BJT Common-Emitter Output Characteristics (I_C vs V_CE)
Collector characteristic curves with base current parameter I_B, highlighting Cutoff, Active, and Saturation regions.
BJT Operating Regions & DC Load Line Analysis
Q-point biasing, DC load line slope -1/R_C, maximum undistorted output voltage swing, and thermal stability.
BJT Common-Emitter Small-Signal Voltage Amplifier
Voltage gain A_v = -g_m * (R_C || R_L), 180-degree phase inversion, input/output impedance, and emitter bypass capacitor effects.
BJT Common-Base High-Frequency Amplifier
Unity current gain, non-inverting high voltage gain, low input impedance, and absence of Miller effect for RF amplification.
BJT Common-Collector (Emitter Follower) Buffer
Unity voltage gain, high input impedance, low output impedance, and impedance matching buffer applications.
BJT Digital Switching & Saturated Inverter
Cutoff to saturation transitions, storage time delay, turn-on/turn-off times, and relay/load driver interfacing.
N-Channel MOSFET Drain & Transfer Characteristics
Enhancement-mode MOSFET drain curves (I_D vs V_DS), threshold voltage V_th, transconductance g_m, and pinch-off saturation.
Power MOSFET Fast Switching & Gate Charge Dynamics
Gate capacitance charging, Miller plateau voltage, R_DS(on) conduction losses, and high-side/low-side driver circuits.
CMOS Inverter Transfer Characteristics & Noise Margins
Complementary NMOS and PMOS pair, static power dissipation near zero, voltage transfer characteristic (VTC), and noise margins NM_H/NM_L.
CMOS Dynamic Switching Power & Parasitic Capacitances
Charging and discharging of load capacitance C_L, dynamic power P = C_L * V_DD^2 * f, and short-circuit crowbar current.
Semiconductor Energy Band Diagrams & Fermi Level
Conduction band, valence band, bandgap energy E_g, intrinsic vs extrinsic doping, and Fermi level positioning.
PN-Junction Depletion Region & Built-in Potential
Space charge density distribution, electric field profile, built-in potential barrier V_bi, and junction capacitance.
Temperature Effects on Semiconductor Device Parameters
Thermal generation of electron-hole pairs, temperature coefficient of diode forward drop (-2mV/degC), and thermal runaway.
Inverting Operational Amplifier (Gain A_v = -R_f / R_in)
Virtual ground concept, negative feedback stabilization, inverting voltage amplification, and gain-bandwidth trade-offs.
Non-Inverting Operational Amplifier (A_v = 1 + R_f / R_1)
High input impedance non-inverting amplification, zero phase shift, and negative feedback gain stabilization.
Op-Amp Voltage Follower (Unity Gain Buffer)
Zero loading buffer circuit with A_v = 1, infinite input impedance, and low output impedance for sensor isolation.
Summing Amplifier (Analog Audio Mixer)
Weighted analog addition of multiple input voltages using inverting summing junction.
Difference Amplifier & Common-Mode Rejection Ratio (CMRR)
Differential voltage amplification V_out = (R_2/R_1)*(V_2 - V_1) and rejection of common-mode environmental noise.
Three Op-Amp Precision Instrumentation Amplifier (In-Amp)
Buffered differential amplifier with single resistor gain adjustment R_gain, ultra-high CMRR, and microvolt-level sensor amplification.
Op-Amp Integrator Circuit (Square to Triangle Converter)
Capacitive feedback integration V_out = -1/(R*C) * integral(V_in dt), frequency response rolloff (-20dB/dec), and DC drift saturation.
Op-Amp Differentiator Circuit & Noise Suppression
Capacitive input differentiation V_out = -R*C * (dV_in / dt), high-frequency noise sensitivity, and practical series resistor stabilization.
Open-Loop Voltage Comparator & Zero-Crossing Detector
Open-loop high gain switching, rail-to-rail saturation, reference voltage thresholding, and zero-crossing detection.
Schmitt Trigger (Inverting & Non-Inverting with Hysteresis)
Positive feedback comparator creating upper (V_UTP) and lower (V_LTP) trigger thresholds, eliminating noise chattering.
Active First-Order & Second-Order Low-Pass Filter (Sallen-Key)
Butterworth low-pass filter response, cutoff frequency f_c = 1/(2pi*R*C), -20dB/-40dB per decade rolloff, and zero passband loading.
Active High-Pass Filter (First & Second Order)
Active HPF topology passing high frequencies while attenuating DC and low-frequency hum.
Active Band-Pass Filter (Multiple Feedback Topology)
Center frequency f_0, bandwidth B, and quality factor Q selection for selective audio and radio frequency tuning.
Active Twin-T Notch Filter (Hum Eliminator)
Deep attenuation notch at 50Hz/60Hz to eliminate interference while preserving adjacent signal harmonics.
RC Phase-Shift Oscillator (Sinusoidal Wave Generator)
Barkhausen criterion, 3-stage RC feedback ladder each providing 60-degree phase shift (total 180 deg), and inverting amplifier gain A_v >= 29.
Wien-Bridge Oscillator with Non-Linear Amplitude Stabilization
Lead-lag network providing zero phase shift at f_0 = 1/(2pi*R*C), required gain A_v = 3, and automatic gain control (AGC) lamp/diode stabilization.
LC Tank Oscillators (Colpitts & Hartley RF Generators)
High-frequency LC resonant tank circuits, capacitive tapped divider (Colpitts) vs inductive tapped divider (Hartley) feedback.
Op-Amp Open-Loop & Closed-Loop Frequency Response
Internal compensation dominant pole, unity-gain bandwidth product (GBWP), open-loop gain rolloff, and closed-loop bandwidth expansion.
Op-Amp Slew Rate & Large-Signal Distortion
Internal compensation capacitor charging rate limit SR = dV/dt, triangular distortion of high-frequency sine waves, and full-power bandwidth.
Negative Feedback Stability, Phase Margin & Nyquist Criterion
Loop gain T = A*beta, gain margin, phase margin, Barkhausen instability, and capacitive load compensation.
Discrete Logic Gates Explorer (AND, OR, NOT, XOR, NAND, NOR, XNOR)
Interactive discrete logic gates, truth table evaluation, toggle switch inputs, output LEDs, and Boolean algebraic identity proofs.
Universal Gate Realization (NAND & NOR Completeness)
Construct NOT, AND, OR, and XOR functions exclusively using universal NAND or NOR gate topologies.
Half Adder & Full Adder 2D Circuit Laboratory
Interactive 2D circuit editor for binary addition: Half Adder (XOR + AND), Full Adder (2 HAs + OR), automated truth-table verification, and multi-channel logic analysis.
Half Subtractor & Full Subtractor Binary Arithmetic
Binary subtraction, Difference bit D = A xor B xor Bin, Borrow bit B_out, and 2s complement equivalence.
Multiplexers (MUX 2:1, 4:1, 8:1) & Demultiplexers
Data selection, address line decoding, digital steering, and arbitrary Boolean function implementation using MUX chips.
Binary Encoders, Priority Encoders & BCD Decoders
Converting active input lines to binary codes, priority resolution for concurrent inputs, and 3-to-8 line address decoders.
Binary-to-Gray and Gray-to-Binary Code Converters
Single-bit transition Gray code encoding for rotary shaft encoders, mechanical debounce, and XOR ladder converters.
Digital Magnitude Comparators (4-Bit A > B, A = B, A < B)
Bitwise equality and magnitude comparison, cascading multiple 4-bit comparators for 8-bit word evaluation.
Parity Bit Generators & Error Detection Checkers
Even and odd parity tree synthesis with XOR gate trees, single-bit error detection across transmission channels.
SR Latch & Clocked SR Flip-Flop (Race Condition Analysis)
Bistable multivibrator cross-coupled NAND/NOR gates, transparent latch operation, clock gating, and invalid S=1, R=1 state.
Edge-Triggered D Flip-Flop & Master-Slave Register
Positive/negative edge triggering, setup time t_su, hold time t_h, and multi-bit data register latching.
JK Flip-Flop & Master-Slave Race-Around Prevention
Elimination of invalid state using feedback to inputs, Toggle mode when J=1, K=1, and Master-Slave isolation.
T Flip-Flop & Binary Frequency Dividers
Toggle flip-flop, binary ripple counting, cascaded frequency divider stages, and clock prescalers.
Universal Shift Registers (SISO, SIPO, PISO, PIPO)
Serial-in serial-out, serial-in parallel-out, parallel-in serial-out, bidirectional shifting, and serial communication serialization.
Ring Counters and Twisted Johnson Counters
Circulating one-hot shift ring counters, self-starting logic, and 2N-state Johnson mobius counters with decoding logic.
Asynchronous Ripple Counters & Propagation Skew
Modulo-N ripple counters, cumulative flip-flop propagation delay, clock skew, and transient decoding glitches.
Synchronous Up/Down Counters with Common Clock
Zero cumulative clock skew using parallel clocked flip-flops, lookahead carry logic, and programmable count sequences.
Finite State Machine (FSM) Sequence Detectors (Mealy vs Moore)
Design of Mealy and Moore state machines detecting overlapping bit sequences (e.g. 1011), state transition tables, and state minimization.
Timing Diagrams, Static Hazards & Glitch Elimination
Static-1 and static-0 hazards caused by unequal path propagation delays, and elimination via consensus terms on K-maps.
4-Bit Arithmetic Logic Unit (ALU 74181 Architecture)
Construction of 4-bit ALU performing 16 arithmetic operations (Add, Sub, Inc) and 16 logic operations (AND, OR, XOR, NOT) with status flags (Z, C, V, N).
Standard Continuous and Discrete Time Signals
Impulse (Dirac delta), Unit Step, Ramp, Exponential, and Sinc functions in continuous and discrete domains.
Continuous and Discrete Convolution (LTI Systems)
Graphical convolution: flip, shift, multiply, and integrate y(t) = x(t) * h(t) for arbitrary input signals and impulse responses.
Nyquist-Shannon Sampling Theorem & Aliasing Demonstration
Sampling continuous signals at rate f_s, Nyquist criterion f_s >= 2*f_max, spectrum replication, and audio aliasing distortion.
Fourier Series Synthesis of Periodic Waveforms
Decomposition of square, triangle, and sawtooth waves into harmonic sine and cosine series, Gibbs phenomenon at discontinuities.
Laplace Transform, Pole-Zero Plots & System Stability
S-plane pole and zero locations, region of convergence (ROC), impulse response decay, and BIBO stability criteria in the left half plane.
Z-Transform, Unit Circle & Discrete System Frequency Response
Mapping from s-plane to z-plane z = e^(sT), unit circle stability (|p_i| < 1), and discrete transfer function H(z) evaluation.
Discrete Fourier Transform (DFT) & Fast Fourier Transform (FFT)
Radix-2 Cooley-Tukey FFT algorithm, O(N log N) computational efficiency, frequency bin resolution, and spectral leakage.
Windowing Functions (Rectangular, Hanning, Hamming, Blackman)
Spectral leakage reduction using non-rectangular window functions, main lobe width vs side lobe suppression trade-offs.
Finite Impulse Response (FIR) Filter Design (Window Method)
Linear phase digital filter synthesis, ideal sinc impulse response truncation, windowing design method, and tap coefficient generation.
Infinite Impulse Response (IIR) Filter Design (Bilinear Transform)
Butterworth and Chebyshev IIR digital filters via Bilinear Transform, frequency warping compensation, and feedback stability.
Amplitude Modulation (AM) & Envelope Detection
Double Sideband Full Carrier (DSB-FC), modulation index m, overmodulation distortion, sideband power distribution, and diode envelope detector.
Frequency Modulation (FM) & Carson Bandwidth Rule
Frequency deviation delta_f, modulation index beta, Bessel function sideband distribution, Carson bandwidth rule, and phase-locked loop (PLL) demodulation.
Digital Modulation Schemes (BPSK, QPSK, 16-QAM Constellations)
I/Q constellation diagrams, phase shifts, bit mapping, symbol rate, carrier recovery, and Additive White Gaussian Noise (AWGN) channel degradation.
Eye Diagrams & Intersymbol Interference (ISI)
Overlaid oscilloscope traces of digital pulse stream, eye height (noise margin), eye width (timing jitter), zero-crossing jitter, and raised cosine Nyquist pulse shaping.
Microcontroller Digital GPIO Interfacing & Button Debouncing
Push-pull vs open-drain outputs, internal pull-up/pull-down resistors, mechanical switch contact bounce, and software debouncing algorithms.
Pulse-Width Modulation (PWM) Duty Cycle & Motor Control
Timer-driven PWM generation, duty cycle modulation, average voltage delivery, H-bridge DC motor speed and direction control, and LED brightness regulation.
UART Serial Protocol Framing & Baud Rate Synchronization
Asynchronous serial data framing: start bit, 8 data bits, parity bit, stop bit, baud rate clock mismatch tolerance, and FIFO buffer overflow.
Synchronous Serial Buses (SPI vs I2C Two-Wire Protocol)
Comparison of 4-wire high-speed SPI (MOSI, MISO, SCK, CS) and 2-wire open-drain I2C (SDA, SCL with ACK/NACK and slave 7-bit addressing).
Half-Wave Dipole Antenna & 3D Radiation Pattern
Resonant length lambda/2, current and voltage standing waves along antenna arms, radiation resistance (73 Ohm), and 3D toroidal donut radiation pattern.
Friis Transmission Equation & Free-Space Path Loss
Inverse-square law power density decay, transmit/receive antenna gains, link budget calculations, and received power P_r in dBm.
Hamming Code (7,4) Single Error Correction & Double Detection
Generator matrix G, parity-check matrix H, syndrome decoding vector, and automatic single-bit error localization and correction.
Shannon Entropy & Channel Capacity Limit (Shannon-Hartley)
Information entropy H(X) = -sum(p_i * log2 p_i), channel capacity C = B * log2(1 + SNR), and theoretical bandwidth-power trade-offs.
Virtual Digital Multimeter (Voltage, Current, Resistance, Continuity)
Comprehensive 4.5-digit benchtop digital multimeter with auto-ranging, DC/AC voltage, current shunts, resistance bridge, and continuity beeper.
Dual-Trace Digital Storage Oscilloscope (DSO & X-Y Lissajous)
Dual-channel oscilloscope with calibrated timebase, volts/division dials, trigger edge/level controls, automated V_pp/frequency measurements, and X-Y Lissajous figures.
Precision Benchtop Function Generator (Sine, Square, Triangle)
Direct digital synthesis (DDS) waveform generator with frequency range from 0.1Hz to 1MHz, variable amplitude, DC offset, and duty cycle.
Single-Phase Transformer Open & Short Circuit Tests
Electrical machines laboratory. Perform no-load O.C. test and full-load S.C. test to extract core loss resistance Rc, magnetizing reactance Xm, equivalent impedance, and efficiency curve.
Series RLC Circuit AC Resonance & Frequency Response
AC circuit resonance testbench. Sweep frequency from 100 Hz to 1500 Hz to observe resonance peak, minimum impedance Z = R, Quality Factor Q, and phasor phase angles.
DC Shunt Motor Speed Control & Torque-Speed Characteristics
Simulate speed control of DC shunt motors via armature voltage variation and field flux weakening, back-EMF, and torque-speed regulation.
3-Phase Power & Power Factor Measurement by Two-Wattmeter Method
Measure total active power and load power factor across balanced 3-phase star/delta AC systems using two electrodynamometer wattmeters.
Alternator Voltage Regulation by Synchronous Impedance Method
Determine synchronous impedance Zs from Open-Circuit (OCC) and Short-Circuit (SCC) tests, and calculate percentage voltage regulation.
BJT Common Emitter (CE) Input & Output Characteristics
Plot input and output family of characteristic curves of BJT in common emitter configuration, Early voltage VA, and small-signal parameters.
Operational Amplifiers: Inverting, Non-Inverting, Summing & Integrator
Verify linear operational amplifier circuit topologies, virtual ground concept, closed-loop voltage gain, summing nodes, and integrator waveforms.