Inside the CPU: Microarchitecture & Datapath Studio
Step through Fetch, Decode, Execute, Memory, and Write Back. Observe real-time RTL micro-operations, active bus wires, register states, pipeline hazard stalls, and cache hit/miss timing.
Speed:600ms
Cycle: 0
Active Stage:FETCH
IR: —
Fetch UnitSTAGE 1
PC:0x00 (0)
MAR:0x00
MDR:0x00
Control UnitSTAGE 2
Opcode:
IDLE
Operands:
none
ALU & FlagsSTAGE 3
ALU Out:0
Z:0
C:0
S:0
V:0
Memory & WBSTAGE 4 & 5
Cache Hit:—
Executed:0 inst
RTL Micro-Operations (0)
- No micro-operations currently executing
Active Hardware Control Signals (0)
No active control signals
8-Bit Register File (R0 – R7)Highlighted on modified cycle
R0
0
0x00
R1
0
0x00
R2
0
0x00
R3
0
0x00
R4
0
0x00
R5
0
0x00
R6
0
0x00
R7
0
0x00
Educational CPU Experiments
Instruction ROM (256-Word)5 instructions
0x00MOV R1, 15
[00 01 00 0F]
0x01MOV R2, 10
[00 02 00 0A]
0x02ADD R1, R2
[03 01 01 02]
0x03OUT R1
[13 01 01]
0x04HALT
[15]